Efficient Design of Multiplier Using Adder Compressors

Abstract

Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improving the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In This paper first we presents an approach towards the reduction of delay in the Wallace tree multipliers by using 4:2 compressors along with full-adders and half-adders, in the partial product reduction stage. After, this paper proposes to design efficient 4-bit and 8-bit Wallace Tree Multiplier using 8-2 and 4-2 adder compressors. Verilog HDL is used for the programming and XILINX 14.7 for the synthesis and simulation. Finally, the proposed design is achieved to get very efficient results.