Reduction of Static Power in CMOS Circuits by Using Biasing and Body Biasing Techniques

Abstract

The VLSI design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a major problem in modern VLSI design. The market of portable, battery operated computing devices has grown rapidly in recent years and so the need for energy efficient design. The mobile computing devices are inactive for a long time and active only for a brief amount of time. So during the inactive state, the devices keep consuming certain power which is dominated by the leakage power consumption of all the components. Various methods have been existed to reduce the leakage power like Power Gating Architecture and Multimode Power Gating Architecture. Power Gating Architecture was presented to support Multiple Power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme suffers from high wakeup time. Recently, a Multimode Power Gating method is used where the wake up time is reduced than the Power Gating Architecture method but the leakage power increases. To reduce static power reduction use low supply voltage and low threshold voltage without losing speed performance. The drawback in Multimode Power Gating method is increase in delay. I proposed a the Body Biasing method that can be combined with Multimode Power Gating method to offer further Static Power Reduction benefits in Standby mode. The Body Biasing requires less design effort and offers greater leakage power reduction than the Multimode Power Gating method. Analysis and extensive simulation results demonstrate the effectiveness of the Body Biasing design.