AN OPTIMIZED TRUNCATED MULTIPLEXER BASED MULTIPLIER TO REDUCE TRUNACTION ERROR

Abstract

This paper proposes a novel architecture for the multiplier based architecture on multiplexers that aim for a reduction of truncation error. The design of error efficient truncated and low power multiplier is essential for VLSI implementation. Several traditional efficient array and parallel multipliers have exist to boost the speed of the device and also to reduce the area and power dissipation.