Use of memories and programmable logic arrays for asynchronous CAM

Abstract

in this paper a new algorithm is proposed in low power content addressable memory (CAM), which provides association between input tag and corresponding address of output data. The proposed architecture mainly depends on the sparse clustered network which is obtained from binary connections. This binary connections will eliminates most of the parallel comparison performed during a search. So, when we compare with conventional low power CAM design, the dynamic energy consumption of proposed design is significantly low. When an input tag is given to the proposed architecture computes a few possibilities for the location of matched tag and it performs the comparison on them to locate a single valid match. Now, for the purpose of simulation, CMOS technology is used. In this we discussed mainly about the design methodology which depends mainly upon the silicon area and power budgets and performance requirements.