High-Speed Truncated Roba Multiplier for Energy-Efficient Digital Signal Processing

Abstract

this paper, we propose an approximateMultiplier that is high speed yet energy efficient. The truncated multiplier, design is implemented by jointly considering the deletion, reduction, truncation, and final addition of PP bits. It is observed that the results of standard parallel multiplier and then compare this result with truncated multiplier which is approximately same. It is analysed that area required for implementation of truncated multiplier reduces to large extent as compare to standard parallel multiplier. The efficiency of the proposed multiplier is evaluated by comparing its performance with those of some approximate and accurate multipliers using different design parameters.