Design A High Speed Parallel Prefix Adder for Communication

Abstract

In this paper, a well-known regular and modular parallel prefix adder is analysed by using residue number system reverse converters. To achieve high speed reverse converters, VLSI is implemented. Because of this there is a reduction in delay and area, as well as high power consumption is obtained. To avoid the high power consumption obtained in the system, a hybrid parallel prefix adders is used. This produces better trade of between delay and power consumption.