A Smooth Strategy For Design Of Low Power Sequential System Using Multi Bit Flip-Flop

Abstract

The major dynamic power consumers in computing and consumer electronics products is thesystem’s clock signal, typically responsible for 30%–70% of the total dynamic power consumption. Clock gatingis a predominant technique used for power saving.  The Data driven clock gating is used for reduce powerconsumption in synchronous circuits .Common clock gating is used for power saving. However clock gatingstill. leaves larger amount of redundant clock pulses. Multibit flip-flop is also used to reduce powerconsumption .Using of Multibit Flip-Flop method is to eliminate the total inverter number by sharing theinverters in the flip-flop .Combination of Multibit Flip-Flop with Data driven clock gating will increase thefurther power saving. Xilinx software tool and quatrus II for power analysis is used for implementing thisproposed system