Efficient Multi-Ternary Digit Multiplier Design in Cntfet Technology Using Low-Complexity Adder Cells

Shaik kaleemullah, Patan Babjan

Abstract


As the scaling of Si MOSFET approaches towards its limiting value, new
alternatives are coming up to overcome these limitations, CNTFET has been reviewed. This paper presents a multiternary digit (trit) multiplier design in Carbon Nanotube Field Effect Transistor (CNTFET) technology using unary operators of multivalued logic. 

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