Efficient Multi-Ternary Digit Multiplier Design in Cntfet Technology Using Low-Complexity Adder Cells
Abstract
As the scaling of Si MOSFET approaches towards its limiting value, new
alternatives are coming up to overcome these limitations, CNTFET has been reviewed. This paper presents a multiternary digit (trit) multiplier design in Carbon Nanotube Field Effect Transistor (CNTFET) technology using unary operators of multivalued logic.
alternatives are coming up to overcome these limitations, CNTFET has been reviewed. This paper presents a multiternary digit (trit) multiplier design in Carbon Nanotube Field Effect Transistor (CNTFET) technology using unary operators of multivalued logic.
Full Text:
PDFCopyright (c) 2018 Edupedia Publications Pvt Ltd
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
All published Articles are Open Access at https://journals.pen2print.org/index.php/ijr/
Paper submission: ijr@pen2print.org