Low Power Vlsi Architecture For Adiabatic Offset Encoder

Abstract

Basically in high video efficiency coding (HVEC), a sample adaptive offset is used as in loop filtering block. This increases the compression efficiency in computer graphics up to 23%. So exhaustive operations are required to optimize the SAO parameters. In this paper a low cost high throughput VLSI implementation is proposed for the parameter estimation phase. Here the proposed architecture reduces the cost in terms of gates count and it is prototyped using 65nm CMOS technology.