Design of Disorder and Fault Tolerant Non-volatile Spintronic Turn Flops

Abstract

With technology down scaling, static power has become one of the biggest challenges in a system on chip. Normally off computing using non-volatile (NV) sequential elements is a promising solution to address this challenge. Generally, various NV shadow flip-flop architectures have been introduced in which magnetic tunnel junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible for manufacturing defects than their CMOS counterparts.