Design of a High Speed Multiplier by Using Ahl

Abstract

Digital multipliers are among the most critical arithmetic functional units. Such as the addition, subtraction, multiplication, division. The overall performance of these systems depends on the throughput of the multiplier, and to design the multiplier speed.  In the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this project VLSI design of a high speed AHL based multiplier has been proposed. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. The proposed architecture can be applied to a column-bypassing multiplier. The experimental results show that our proposed architecture with 64 × 64 column-bypassing multipliers