Design a Novel FFT for Fault Tolerant Razor Flip Flop

Abstract

 In this paper, a cryptographic algorithm is used to perform the time consuming operations like modular multiplication operation. The time required to implement the modular multiplication is more than 75% of RSA. To minimize the delay and increase the throughput fast multiplier architectures are used. But this architectures occupy large area and gives less efficiency. So, to get high efficiency improved FFT-based Montgomery modular multiplication (MMM) algorithm is used. In existed system zero padding operation is performed to compute the modular multiplication steps.In this proposed architecture single and double butterfly structures are designed to get low area-latency solutions and these are implemented on Xilinx SPARTAN3E FPGAs.