Design a High Speed and Energy Efficient Novel FFT Using CSKA

Abstract

The DFT (Discrete Fourier Transform) is a significant technique in the fields such as Telecommunications and Digital Signal Processing (DSP). An efficient algorithm for enumerating the DFT and its inverse is Fast Fourier Transform (FFT). The FFT processor plays a key role in the field of communication systems such as Digital Video or Audio Broadcasting, Wireless LAN with Standards of IEEE 802.11, High Speed Digital Subscriber Lines etc. The existed structure utilizes AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) compound gates for the skip logic. The existed system is complex in area. Hence, we propose an algorithm which is area efficient and consumed delay in previous algorithm. The proposed design is implementation in Xilinx software.

KEY TERMS:  Single Path Delay Feedback (SDF), Serial in Serial out Shift Register, Fast Fourier Transform (FFT), CSKA, Folding Technique.