Design of Power Droop Reduction Scan Based Rc Logic Bist

Abstract

Built-in self-test (BIST) is an attractive approach to detect delay faults because of its inherent support for at-speed test. RC logic BIST (RCLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for RCLBIST schemes has increased. However, an extension to delay fault testing is not trivial as this necessitates the application of pattern pairs. As a consequence, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. With this in mind, we consider the RC fault model, which is widely used for complexity reasons, and an extension of a RCLBIST scheme for transition fault testing is presented. Rows and column logic BIST is applied to the memory array to make the error free operation. As in single vector address memories faces many problems like stuck at faults, to overcome this we are applying two vector addresses for memories. The two vectors are called as row and column. The total simulation is done in xilinx 14.7.

Index Terms: Power Droop (PD), Stuck-at Faults, Built-in self-test (BIST), Row Column Logic BIST (RCLBIST)