Design a Redundant Adaptive Multiplier for High Speed Applications

Abstract

In this paper, our focus is on digit-level architectures for RBmultipliers.  Basically, redundant multiplier requires large number of hardware resources while embedding the F2m in cyclotomic field.  Two variants of multiplication algorithms along with their corresponding architecture are presented here.It is shown that the proposed architectures have highly regular structures and thus suitable for hardware implementation.   Comparisons with existing digit-level RB architectures the proposed architectures outperform the area-delay product as a measure of performance.  At last it can observe that the proposed system gives better redundancy compared to existed system.