Implementation Of High Speed Sense Amplifier For 6 T Sram With Highly Configurable Low-Voltage Write-Ability Assist Method

Abstract

Abstract: The Sense amplifier’s sense delay is one important parameter to measure the speed of SRAM memory cell. The sense delay depends on the amplifier reaction time. This delay parameter is more vulnerable to device variations, temperature and supply voltage variations. A latch type voltage controlled sense amplifier considered among all the offered current and voltage sense amplifier types for data sensing from the SRAM cell. The modified conventional latch type voltage controlled coupling capacitor based sense amplifier is implemented to improve the performance of the memory cell. The proposed circuit scheme will provide the reasonable negative voltage at the sense amplifier virtual ground, then the driving capability of the pull down (NMOS) transistors is increased, hence it made the sense amplifier faster. The conventional sense amplifier is compared with proposed coupling capacitor sense amplifier. From the experimental results, it is observed that coupling capacitor based sense amplifier circuit scheme will decrease the sense amplifier reaction time and access the data fast. The result shows, the proposed scheme provides the improvement of sense delay reduction of 198ps at SS/-40 C/1.2v and 18ps at FF/127 C/1.2v process corners at the cost of power consumption

Key words: Coupling Capacitor SRAM cell Offset Reaction time