Design of High Speed Pre-Encoded Multiplier Based On NR4SD Encoding Using Han-Carlson Adder

Abstract

In this paper, we introduce architecture of high speed Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the Han-Carlson adder (HCA), is used at the addition of partial products and proposed leading to a multiplier design with less area at final sum stage and high speed implementation compared to NR4SD multiplier using Carry Save Adder (CSA). NR4SD multiplier is also area efficient compared to MB multiplier, which uses the digit values {-2,-1,0,+1} or {-1,0,+1,+2} that leads to fast multiplication than the conventional Modified Booth Multiplier. These pre-encoded multipliers are based on off-line encoding of generating less number of coefficients for Digital Signal Processing (DSP) applications. The Proposed Multiplier is fast requires less area with efficient power usage.