A High-Speed Data Transmission of an Redundant Signed Digit -Based Ecc Processor

Abstract

In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor primarily based on redundant signed digit illustration is proposed. The processor employs extensive pipelining techniques for Karatsuba–Ofman approach to obtain excessive throughput multiplication. Furthermore, an efficient modular adder without comparison and a high throughput modular divider, which results in a short data-path for maximized frequency, are implemented. The examination of speed and area overhead among various ECC plans legitimizes the cost-adequacy of the proposed ECC architecture with its design procedure. The Xilinx virtex 5 field programmable gate array has been utilized. The usefulness of the FPGA will be checked by utilizing chip scope pro analyzer. Further the processor is actualized in ASIC CMOS innovation.