A Review on Power optimization of BIST circuit using low power LFSR

Abstract

: In most number of electronic systems that are used in safety critical applications circuit testing has to be performed periodically. For these systems power dissipation due to BIST [built in self test] represents a significant percentage of overall power dissipation. The power dissipation during the test mode is 200% more than in normal mode. So, to reduce the power dissipation during the test mode for BIST circuit, we are using a low power LFSR. The correlation between consecutive patterns are higher in normal mode than during testing so, by using LPLFSR we are reducing the transitions between consecutive patterns generated by the conventional LFSR.