Design of Area and Power Efficient VLSI Architecture for MAC Based FIR Filter

Abstract

 Finite Impulse Response (FIR) filters are the most popular type filters in a typical digital filter application on a Digital signal processing (DSP) reads a input samples from an A/D converter, performs the mathematical manipulations dictated by theory for the required filter type and outputs the result via a D/A converter. Digital filters uses finite precision to represent signals and are differ from analog filters as digital filters uses finite precision arithmetic to compute the filter response. In this project, FIR filter is implemented in Xilinx ISE using VERILOG language. VERILOG coding for the FIR filter is implemented in this project and waveforms are observed through simulation. Due to the explosive growth of multimedia application, the demand for high performance and low power DSP is getting higher and higher. Most widely used fundamental device performed in DSP system is FIR digital filter.Being the critical implementation, FIR filter design using MAC implementation continues to be a critical area of on-going research activities. For

better performance it is good direction to optimize power consumption, reduction in computational complexity as well as area optimization of FIR digital filter.