High Speed and Low Power VLSI Architecture for Inexact Speculative Adder

Abstract

 This paper presents carry-look ahead adder (CLA) based design of the contemporary inexact-speculative adder (ISA) which is fine grain pipelined to include few logic gates along its critical path .Approximate computing is an efficient approach for error-tolerant applications because it can trade off accuracy for speed. Addition is a key fundamental function for these applications. In this project, proposing with a high speed accuracy-configurable adder . The proposed adder is based on the conventional carry look-ahead adder, and its configurability of accuracy is realized by carry propagation at runtime. Compared with the conventional carry skip adder, the proposed experimental result demonstrates the achievement of the original purpose of optimizing speed simultaneously without reducing the accuracy.