Low Power Parallel VLSI Architecture for Mbist

Abstract

This paper will present a flexible Memory Builtin Self-Test (MBIST) designed to be easily adaptable to specific memory configurations and user requirements. Its RTL code is generated by means of programming scripts that provide an easy to read code without the use of complex compiler directives. The basic architecture can be adapted to different schemes of test such as parallel, in which all the memories are tested concurrently, or sequential, in which the memories are tested one at the time. Linear-feedback shift register (LFSR) counters however a counter design based on multiple LFSR stages is the proposed designs that have been shown to be well suited to applications requiring large arrays of counters and can improve the area and performance compared with conventional binary counters, which are used in existed design.