VLSI Architectures for 8 Bit Data Comparators for Rank Ordering Image Applications

C Satish Babu, S. Ashok Reddy, Malli karjuna


The main objective of the proposed work is to develop a new Data comparator which gives an economical solution for sorting / Rank ordering networks on the basis of speed, power, and area. The proposed work comprises a design of six different comparators for 8 -bit comparison. The performances of these six different comparators were targeted for XCV1000-4bg560 using Xilinx 7.1i compiler tool using VHDL. It was found that Carry select logic based data comparator requires less area and suitable for reduced area applications. The Conventional bit wise logic based data comparator operated with less delay. Hence this architecture can be used for high speed application.

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