A High-Speed FPGA Implementation of an RSD-Based ECC Processor

Abstract

In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba–Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high throughput modular divider, which results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs singlepoint multiplication employing points in affine coordinates in 2.26 ms and runs at a maximum requency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array.