Hardware Modeling of Sorting Mechanism for Finding First Maxima

Kante Raj Kumar, V. Thrimurthulu

Abstract


with this document, we have proposed a complete VLSI model of sorting mechanism to find first maxima/minima values using (BWA) Bit Wise And architecture.In this effort a parallel radix-sort-based VLSI architecture for finding the first W maximum (or minimum) values is proposed.

Keywords


Sorting; Bit Wise and Operation; verilog; RTL description

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Copyright (c) 2015 Kante Raj Kumar, V. Thrimurthulu

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