Realization of Data Encoding Schemes in Network on Chip Using Verilog HDI

Abstract

Power has become a paramount design criterion in modern system designs, especially in portable battery-driven applications. A paramount portion of total power dissipation is due to the transitions on the off-chip address buses. This is because of the astronomically immense switching capacitances associated with these bus lines. There are many encoding schemes in the literature that achieve an immensely colossal reduction in transition activity on the ordinant dictation address bus. However, on data and multiplexed address buses, none of the subsisting schemes consistently achieve consequential reduction in transition activity. Additionally, many of the subsisting techniques integrate redundancy in space and/or time. In this paper, novel encoding schemes are proposed that significantly reduce transitions on these buses without integrating redundancy in space or time. Additionally, for applications with tight delay constraints, configurations with minimal delay overhead while still achieving paramount reduction in transition activity are proposed. Results show that, for sundry benchmark programs, these techniques achieve reduction of up to 54% in transition activity on a data address bus. On a multiplexed address bus, there is a reduction of up to 61% utilizing our techniques. The proposed schemes are then compared with the subsisting schemes. It is optically discerned that on an average, the reductions achieved by our techniques are twice those obtained utilizing the current scheme on a data address bus and 55% more than those for multiplexed address bus.