Optimized Reversible Vedic multipliers for High Speed Low Power Operations

K. Parameswarareddy, B. Balasubbanna


Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. It’s simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications. For exiting system we are using 4-bit multiplier ,but the given proposed system we are implementing 8-bit multiplier using reversible vedic mathematics approach as shown in above diagram.


Optimized Reversible; Vedic multipliers; High Speed Low Power Operations

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Copyright (c) 2015 K. Parameswarareddy, B. Balasubbanna

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