Design and Verification

Abstract

Advanced Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In most of the previous works subbytes and inverse subbytes are implemented in Separate Modules using lookup table method. In this paper we used combinational logic which helps for making inner round pipelining in an efficient manner. Furthermore, composite field arithmetic helped in obtaining lesser area. Using proposed architecture, a fully sub pipelined encryptor/ decryptor with 3 substage pipelining in each round can achieve a throughput of 25.89Gbps on Xilinx xc5vlx110t-1 device which is faster.
This AES design was implemented using Verilog HDL and synthesized with Xilinx ISE using Spartran3 Xilinx Family , Simulation and Verification was done using Mentor-Graphics ModelSim-6.5e and achieved the maximum through put.