Design and Implementation an Efficient Hardware Utilization for Testing Applications by UART with BIST

Abstract

BIST is a design-for-testability technique that places the testing functions physically with the circuit under test (CUT). The basic BIST architecture requires the addition of three blocks to a digital circuit which are a test pattern generator, a response analyzer, and a test controller. The test pattern generator generates the test patterns for the CUT. An LFSR is used as a pattern generator to generate the patterns. A typical response analyzer is a comparator with stored responses. It analyzes the test responses to determine correctness of the CUT. A test control block is necessary to activate the test and analyze the responses. However, in general, several test-related functions can be executed through a test controller circuit. In this project, the design is implemented by using of a LFSR. In the initial state, the LFSR output will be set to 0. Later, on occurrence of each clock, the value will be incremented by 1, but when the output reaches to the value of 511, again the LFSR resets to 0. Thus the 9-bit LFSR is capable to generate all possible Test patterns. The patterns generated by the LFSR are applied to the UART (CUT).In the UART it is required to perform an addition operation at one instance. So, we implemented the addition operation by using Reversible Logic Gates. By using this technique, power consumption is reduced compared with normal adders. This project is implemented by VERILOG HDL in Xilinx 12.3i with the device XC3S500E-5fg320.