Implementation and Comparison of Effective Area Efficient Architectures for CSLA

Yamarthi Yogananda Prasad, B S. Madhuri, S. Neelima

Abstract


The results analysis shows that the proposed modified BEC CSLA structure is better than the regular BEC SQRT CSLA. This paper introduces an unique method that replaces the BEC using common Boolean logic. This paper proposes an efficient method which replaces the BEC using D latch. Experimental results are compared and the result analysis shows that the proposed architecture achieves the three folded advantages in terms of area, delay and power.

Keywords


Carry Select Adder(CSLA); area efficient; Field Programmable gate array(FPGA); Boolean Logic; Square Carry select adder root CSLA(SQRT CSLA)

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Copyright (c) 2015 Yamarthi Yogananda Prasad, B S. Madhuri, S. Neelima

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