Low-Complexity Low-Latency Architecture for Identical of Data Encoded With Hard Systematic Error-Correcting Codes

Abstract

This issue is more severe when the exaggerated memory cells are part of the configuration memory used for programming the circuit functionality. Grounded on the BWA, the proposed architecture examines whether the incoming data matches the stored data, and if not it aims to locate the erroneous bit and they are corrected. The empirical evaluation proves that the proposed methodology discovers the best examine for consistency issues of memory