Design and Implementation of Efficient Reversible Vedic multiplier for Low Power and High Speed Operations

Abstract

In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications. For exiting system we are using 4-bit multiplier,but the given proposed system we are implementing 8-bit multiplier using reversible vedic mathematics approach as shown in above diagram.