Constraint Random Verification of Network Router for System on Chip Applications

Abstract

The focus of this paper is the actual implementation of Network Router and verifies the functionality of the five port router for network on chip using the latest verification methodologies, Hardware verification Languages(s) and EDA tools and qualifies the design for synthesis and implementation. This Router design contains four output ports and one input port, it is packet based protocol. This design consists of registers, FSM and FIFO’s. The verification goes on it finds functional coverage of the Network router by using system Verilog.