FPGA Implementation of New Architecture

Abstract

The paper mainly focus on a development of a new architecture of a BCD parallel multiplier that utilizes some properties of two different redundant BCD codes to speed up its computation: the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In this we have developed some new techniques to reduce the latency and area of some previously high-performance implementations. The above developed architecture of has been synthesized a RTL model and given better performance compared to old version multipliers