Design for Exterminating Synchronization Latency Using Sequenced Latching

Abstract

In the present generation where the modern multi-core systems which have a large number of components that operate with different clock domains and communicating through asynchronous interfaces. And due to this interfaces synchronizer circuits are used, which guard against metastability failures but this introduces delay in processing the asynchronous input. Hence we propose a novel method that hides synchronization abeyancy by overlapping it with computation cycles. In this work a method that performs speculative computations during synchronization cycles and hence prevented synchronization time from incurring abeyance. Our methods relies on sequence the latching of data using synchronizer state during synchronization cycles and automatically re-latch if any corrupt data is latched. Synthesis results reveal that our approach achieves average savings of Area, costs and power costs compared to two similar speculative techniques. The Proposed design will be implemented using Verilog HDL.