Design and Development of Reliable Multipliers using Adaptive Hold Logic

Abstract

The multiplication operation speed can be increased by designing different types of multipliers. So, a high performance reliable multiplier is designed to improve the performance of the system. The column bypassing multiplier and row bypassing multipliers which are improved from array multiplier are designed with two different types of adders and embedded into an proposed architecture which consists of Adaptive hold Logic module with Variable latency technique and Razor flip flop to improve the performance. To improve the performance of these two multipliers, we performed the final addition level with Carry look ahead adder. In this paper, we compared 64-bit multipliers designed with ripple carry adder and carry look ahead adder in final addition and the results shown that performance of multiplier with carry look ahead adder was improved.