Performance Analysis of Low Power Decoders Using Reversible Computing

Abstract

In this paper performance analysis of 2:4 reversible decoder is proposed which can provide active high as well as active low outputs. The proposed decoder uses BVF gate, Double Feynman andFredkin gates and Trace circuit to get low power consumption and quantum cost. The proposed gate is fist extended to 4:16 decoder followed by an n-input decoder. The theoretical proposition is verified through Xilinx simulations. A comparison with existing reversible decoders is also included.