Low Complexity Decoding Algorithms and Architectures for Non Binary LDPC Codes

M. Sravan Kumar, A. Satheesh


In this paper we propose an integrated version of EMS (Extended Min-Sum) and layered turbo decoding in Low density Parity Check Codes. Algorithmic complexity and memory problems are the major problem faced in NB-LDPC. This can be reduced by EMS algorithm under logarithm domain in the order of (􀝊m log2 􀝊m).Speed is increased by using layered turbo scheduled decoding algorithm. Efficient implementation of non-binary LDPC decoders is a progressing field which is updated currently. This paper is based on (1) the hardware implementation costs for NB-LDPC decoders with Galois field(8,16,128,256) on FPGA and (2) To set the noise threshold very close to the theoretical maximum (Shannon Limit).
Keywords: NB-LDPC; EMS; layered turbo scheduled decoding algorithm; BP

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Copyright (c) 2015 M. Sravan Kumar, A. Satheesh

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