Reliable Low Power Multiplier Design Using Reduced Replica Redundancy Block

Abstract

We develop a new method for designing a reliable low power multiplier by using algorithmic noise tolerant tecnique. To propose the fixed width RPR to replace the full width RPR block in the ANT design. RPR is a reduced precision replica whose output is taken as the corrected output in case the original system computes error. It reduces the truncation error and then constructs a lower error fixed width Wallace tree multiplier. It is efficient for VLSI implementation. The ANT technique having high accurate, low power consumption and area efficiency. To design the fixed width RPR by using the partial product terms of input correction vector and minor input correction vector to reduce the errors.
Keywords- algorithmic noise tolerant(ANT); reduced precision replica(RPR); fixed width Multiplier