Design of High Speed Hybrid Sqrt Carry Select Adder

Abstract

Power dissipation is one of the most important design objectives in integrated circuits, after speed & area. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers. This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. We present a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption in comparison with Regular CSA, BEC-CSA, CBL-CSA. The design has been synthesized at 90nm process technology targeting using Xilinx 14.7.