Look-Ahead Clock Gating On Novel Auto-Gated Detff Flip-Flops

Panuganti Uma Maheswari, G Mahendra


Gating of the clock signal in VLSI chips is nowadays a mainstream methodology for reducing switching power consumption. several techniques to reduce dynamic power of which clock gating is predominant. clock gating is employed at all levels: system architecture, block design, logic design and gates. three gating methods are known. the most popular is synthesis based on the logic of underlying system. It leaves the majority of clock pulses driving flip flops redundant. The data driven clock gating yields higher power savings but its design methodology is complex. Third method is auto gated flip flops , it is simple but yields small power savings. Our data-driven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow, achieving total power reduction of 15%–20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65 manometer process technologies.
Keywords— Clock Gating; Clock Networks; Dynamic Power Reduction

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Copyright (c) 2015 Panuganti Uma Maheswari, G Mahendra

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