High Speed Vedic Multiplier Designs Using Novel Carry Select Adder

Abstract

A system’s performance is the major part which is dictated by the speed of the multiplier since multiplier is one of the key hardware components in high performance systems, for example, FIR filters, digital signal processors and microprocessors and so forth. Multipliers have the extensive range, long latency and consume considerable power. High speed is accomplished by diminishing carry propagation delay which might set aside less time for execution. Because of its rapid handling capacity, a multiplier is required. The generally happening issues in a multiplier are power dissipation and more delay. So we utilize Vedic multiplier which brings about less delay, in this manner A few multiplier building design expands the proficiency and execution of a framework. In this paper, a 16-bit X 5-bit multiplier is composed utilizing modified carry select adder which is productive to expand the speed of multiplication.
Keywords: High Speed Vedic; Multiplier Designs; Novel Carry; speed of multiplication