Designing Fir Filter Using Modified Look up Table Multiplier

Abstract

With the advancement in device scaling, semiconductor have met the cost, speed and power performance. In addition to that, the projections of the international technology roadmap for semiconductors, the total system on chips content exceeds by 90% in the embedded memories. Besides this, the memory-based computing structures are relatively regular than the multiply–accumulate structures and offer advantages like, greater potential for high-throughput, low-latency implementation and less dynamic power consumption and thus finds its application in DSP processors. Distributed arithmetic (DA)-based computation is widely used because it can be implemented efficiently on memory-based circuits of finite impulse response (FIR) filter where the computation is performed as inner-product of input sample vectors and filter coefficient vector. In this paper, however, we show that the lookup-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the filter coefficients could be an area-efficient. Moreover, two new approaches to LUT-based multiplication is presented, wherein the memory size is reduced to half of the conventional LUT-based multiplication at the cost of  increase in the size of the adders, and additional ∼ (2N×W) NOR gates and ∼(4N×W) NAND-NOR-INVERT gates. LUT multiplier based design of 16-tap FIR filter the area and delay complexities of the multipliers of different word size are to be estimated from the synthesis results.

Keywords: Memory-Based Computing; FIR Filter; LUT Based computing; digital signal processing (DSP) chip; VLSI