A Low Power 32-Bit Ripple Carry Adder Using Dynamic DML CMOS Logic Gates

R. Vijay, M. Damodhar rao


Now a day’s low power consumption plays a vital role in microelectronics. So in terms of power consumption we designed a low power 32-bit ripple carry adder by using dynamic DML CMOS logic gates. Here the 32-bit ripple carry adder previously designed by static CMOS logic gates. In static CMOS logic gates required ‘2n’ gates for ‘n’ variables, where as in dynamic CMOS logic gates require’ n+2’ gates require for ‘n’ variables. So the power consumption in dynamic DML CMOS gates is almost half of the static DML CMOS logic gates. Here, the 32-bit static CMOS ripple adder consumes an 8mw and 32-bit dynamic CMOS full adder consumes a 6.80E-1 mw.This simulations results done by Pspice simulation tool.

Keywords: static CMOS; dynamic CMOS; DML (dual mode logic); Full adder; 32-bit ripple carry adder.

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Copyright (c) 2016 R. Vijay, M. Damodhar rao

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