Ultra Low-Power Scheming of an Efficient Shift Register by Means of Pulsed Latch

Abstract

Shift registers are usually used in lots of applications, such as digital filters and communication receivers. In the recent times, as size of image data maintain to increase because of high demand in support of high quality image data, word length of shift register increases for processing huge image data within image processing Integrated circuits. As the recent trends mandate low power design automation on particularly vast scale for matching the trends of power consumption of the present days as well as future integrated chips. We introduce a low-power as well as area-efficient shift register by means of pulsed latches which is an important solution intended for small area as well as low power consumption. Area as well as power consumption are reduced in the proposed system by replacing flip-flops by means of pulsed latches. The proposed system saves area and power when compared to traditional shift register with flip-flops. The shift registers lessen number of delayed pulsed clock signals significantly, though it increases number of latches because of additional temporary storage latches