Fast Calculation Using Vedic Multiplier with Different Algorithms and High Performance

Abstract

A high speed and low power 16×16 Vedic Multiplier is designed by using low power and high speed changed carry choose adder. This work proposes a high speed Vedic Multiplier primarily based on area, delay and power efficient Carry Choose Adder. In this paper a quick methodology of multiplication based on ancient Indian Vedic arithmetic is proposed. The whole of Vedic arithmetic is based on 16 sutras and manifests a unified structure of arithmetic. Among the varied ways of multiplication in Vedic arithmetic, Urdhava tiryakbhyam is discussed intimately. All the redundant logic operations present in the traditional CSLA are eliminated and proposed a brand new logic formulation for CSLA. The proposed CSLA design involves considerably less space and delay than the recently proposed BEC-based CSLA. The multiplier mentioned here is compared with other multiplier to spotlight the speed and power superiority of the vedic multiplier.