Low Power Asynchronous Domino Logic Pipeline Design Strategy

Abstract

In today’s world pipelining is a key element of

high-performance design. Distributed synchronization is one of the key strengths and one of the major difficulties of synchronous pipelining. It automatically provides elasticity and on-demand power consumption. For that, this project presents a survey on high-throughput and ultra low-power asynchronous pipeline design method targeting to latch-free and extremely fine-grain design. Since they are asynchronous, these pipelines avoid problems related to high-speed clock distribution, such as clock power, clock skew, and rigidity in handling varied environments. The survey is mainly done on the data path logic. The data path may be single-rail, dual-rail or combination of the both logic. Asynchronous pipeline based on constructed critical data-path is combination of both the data path. Critical path compose of dual- rail logic and noncritical enables single-rail logic. Based on this critical data path, the handshake circuits are simplified, which offers the pipeline low power consumption as well as high throughput by reducing the overhead problems. This design is going to be implemented by TANNER EDA simulations model.