An Efficient Implementation of Low Power Three Input Xor/Xnor Gate

Abstract

In this paper, we propose a new three input XOR/XNOR circuit to reduce the delay and power consumption as these circuits is basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. We start with selecting a basic cell including three independent inputs and two complementary outputs. Next we combine this basic cell with various correction and optimization techniques to build a perfect XOR-XNOR circuit with full swing operation. The performance of the XOR-XNOR circuits based on systematic cell design methodology process models at all range of the supply voltage is evaluated by the comparison of the simulation results obtained from MICRO WIND. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.