Sub threshold flip- Flops Design and Simulation for low power VLSI Circuits

Abstract

Power consumption minimisation is constantly required to meet increasing demand for Energy performance requirements. For this, designers of next-generation systems are trying hard to explore new approaches for least possible power consumption. Major factor to reduce the power consumption is Scaling of power supply voltage. To achieve higher drive current and hence better speed, threshold voltage may be reduced but at the cost of increase in the stand-by power. Operating the circuit with a supply voltage lower than the threshold voltage i.e. sub threshold region is the technique to achieve ultra-low power. Sub threshold operation is being examined to stretch low-power circuit designs beyond the normal modes of operation, with the potential for large energy savings. Ultra low-power consumption can be achieved by operating digital circuits with scaled supply voltages. In this report proposed sub threshold circuit is based on GDI (Gate Diffusion Input) - a new technique of low power digital combinational circuit design. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design as compared to other CMOS circuits. Electric Tool is used to design the schematic and layout level diagrams of our project. The LT-SPICE tool will be used for simulation of the Spice code which tests the functionality of our generated layout and schematic blocks.