Energy and discipline effective Implementation for Parallel FIR Filters utilizing FFAs and DA

Abstract

This paper describes the implementation of two parallel FIR filter based on traditional method costs considerable hardware power and area. The Finite Impulse Response (FIR) filters mainly contain delay elements, adders and multipliers. The usage of multipliers in the filter structure leads to increase in area and delay which may results ultimately in low speed and performance. A new design and implementation of two parallel FIR filter structure using Look Up Table (LUT) less Distributed Arithmetic (DA) is proposed in this paper which are beneficial to symmetric coefficients reducing half of the multipliers in sub-filter blocks of two parallel FIR filter. The LUT less method is used to decrease the amount of required memory units in the two parallel filter structure. In proposed structure, the multipliers are replaced with shifters and adders so that adders weight less than multipliers in terms of silicon. Overweigh from the additional adders in pre-processing and post-processing blocks stay fixed along with the filter length and they doesn’t increase with tap length, this is the key merit of proposed filter architectures. Overall, the synthesis result shows that the proposed two parallel FIR structure can save more than 50% of significant power and area of circuit scale and can be applied to different types of filters with different coefficients for its flexibility and high reliability.